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Senior ASIC Design Engineer

PRIMARY RESPONSIBILITY:

The Senior ASIC Engineer will work on complex ASIC and FPGA designs for our point to multipoint wireless products.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

RTL design of digital circuits using VHDL or System Verilog
Frontend design development and integration of large ASIC designs including:
Integration of Processor, Bus, Memory, and Interface IPs and working on chip level integration and verification
RTL design and integration of large functional blocks in the modem - Development, assessment and refinement of RTL design to target power, performance, area and timing goals

Write design documents including high level interface descriptions and design descriptions
Writing test cases and test benches to verify functionality of designs

ESSENTIAL JOB REQUIREMENTS:
Education:  BSEE required / MSEE preferred.
Experience  :  A minimum of 8 years of experience in SoC design and verification is required.


Knowledge, Skills and Abilities:

Working knowledge of CPU buses (AXI, AHB), DDR and Flash memory interfaces, PCIe and Ethernet
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Experience with ARM/ARC/MIPS or DSP embedded processors in SoCs.
Good knowledge of programming in C or C++.
Experience/knowledge in the architecture/RTL design of signal processing wireless protocols including 802.11a/b/g/n/ac or hands-on experience in any of one of LTE/WiMAX/4G preferable
Experience in programming Perl, Python or other scripting language
Good understanding of System Verilog.

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